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dc.contributor.authorPrasanna, G.N. Srinivasaen_US
dc.contributor.authorAgarwal, Ananten_US
dc.contributor.authorMusicus, Bruce R.en_US
dc.date.accessioned2023-03-29T14:36:01Z
dc.date.available2023-03-29T14:36:01Z
dc.date.issued1992-10
dc.identifier.urihttps://hdl.handle.net/1721.1/149192
dc.description.abstractThis paper presents a hierarchical approach for compiling macro dataflow graphs for multiprocessors with local memory. Macro dataflow graphs comprise several nodes (or macros operations) that must be executed subject to prespecified precedence constraints. Programs consisting of multiple nested loops, where the precedence constraints between the loops are known, can be viewed as macro dataflow graphs. The hierarchical compilation approach comprises a processor allocation phase followed by a partitioning phase. In the processor allocation phase, using estimated speedup functions for the macro nodes, computationally efficient techniques establish the sequencing and parallelism of macro operations for close-to-optimal run times. The second phase partitions the computations in each macro node to maximize communication locality for the level of parallelism determined by the processor allocation phase. The same approach can also be used for programs consisting of multiple loop nests, when each of the nested loops can be characterized by a speedup function. These ideas have been implemented in a prototype structure-driven compiler, SDC, for expressions of matrix operations. The paper presents the performance of the compiler for several matrix expressions on a simulator of the Alewife multiprocessor.en_US
dc.relation.ispartofseriesMIT-LCS-TM-466
dc.titleHierarchical Compilation of Macro Dataflow Graphs for Multiprocessors with Local Memoryen_US
dc.identifier.oclc27929937


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