Performance Tradeoffs in Multithreaded Processors
| dc.contributor.author | Agarwal, Anant | en_US |
| dc.date.accessioned | 2023-03-29T15:17:43Z | |
| dc.date.available | 2023-03-29T15:17:43Z | |
| dc.date.issued | 1991-04 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/149704 | |
| dc.description.abstract | High network latencies in large-scale multiprocessors can cause a significant drop in processor utilization. By maintaining multiple process contexts in hardware and switching among them in a few cycles, multithreaded processors can overlap computation with memory accesses and reduce processor idle time. | en_US |
| dc.relation.ispartofseries | MIT-LCS-TR-501 | |
| dc.title | Performance Tradeoffs in Multithreaded Processors | en_US |
| dc.identifier.oclc | 23715074 |
