Exploring Optimal Cost-Performance Designs for RAW processors
| dc.contributor.author | Moritz, Csaba Andras | en_US |
| dc.contributor.author | Yeung, Donald | en_US |
| dc.contributor.author | Agarwal, Anant | en_US |
| dc.date.accessioned | 2023-03-29T15:31:06Z | |
| dc.date.available | 2023-03-29T15:31:06Z | |
| dc.date.issued | 1998-06 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/149877 | |
| dc.description.abstract | The semiconductor industry roadmap projects that advances in VLSI technology will permit more than one billion transistors on a chip by the year 2010. The MIT Raw microprocessor is a proposed architecture that strives to exploit these chip-level resource | en_US |
| dc.relation.ispartofseries | MIT-LCS-TR-754 | |
| dc.title | Exploring Optimal Cost-Performance Designs for RAW processors | en_US |
