Browsing LCS Technical Memos (1974 - 2003) by Author "Agarwal, Anant"
Now showing items 1-13 of 13
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Addressing Partitioned Arrays in Distributed Memory Multiprocessors - the Software Virtual Memory Approach
(1994-12)Harnessing the full performance potential of cache-coherent distributed shared memory multiprocessors without inordinate user effort requires a compilation technology that can automatically manage multiple levels of memory ... -
Closing the Window of Vulnerability in Multiphase Memory Transcations
(1992-06)Multiprocessor architects have begun to explore several mechanisms such as prefetching, context-switching and software-assisted dynamic cache-coherence, which transform single-phase memory transactions in conventional ... -
Compile-time Techniques for Processor Allocation in Macro Dataflow Graphs for Multiprocessors
(1992-06)When compiling a progam consisting of multiple nested loops for execution on a multiprocessor, processor allocation is the problem of determining the number of processors over which to partition each nested loop. This paper ... -
Experience with Fine-grain Synchronization in MIMD Machines for Preconditioned Conjugate Gradient
(1992-10)This paper discusses our experience with fine-grain synchronization for the preconditioned conjugate gradient method using the modified incomplete Cholesky factorization of the coefficient matrix as a preconditioner. This ... -
How to Build Scalable On-Chip ILP Networks for a Decentralized Architecture
(2000-04)The era of billion transistors-on-a-chip is creating a completely different set of design constraints, forcing radically new microprocessor archiecture designs. This paper examines a few of the possible microarchitectures ... -
Limitless Directories: A Scalable Cache Coherence Scheme
(1991-06)Caches enhance the performance of multiprocessors by reducing network traffic and average memory access latency. However, cache-based systems must address the problem of cache coherence. We propose the LimitLESS directory ... -
Memory Assignment for Multiprocessor Caches Through Graph Coloring
(1992-02)It has become apparent that the achieved performance of multiprocessors is heavily dependent upon the quality of the availabel compilers. In this paper we are concerned with compile-time techniques that can be used to ... -
The MIT Alewife Machine: A Large-scale Distributed-memory Multiprocessor
(1991-06)The Alewife multiprocessor project focuses on the architecture and design of a large-scale parallel machine. The machine uses a low dimension direct interconnection network to provide scalable communication band-width, ... -
Modeling Multiprogrammed Caches
This paper presents a simple, yet accurate, model for multiprogrammed caches and validates it against trace-driven simulation. The model takes into account nonstationary behavior of processes and process sharing. By making ... -
Software-Extended Coherent Shared Memory: Performance and Cost
(1993-10)This paper evaluates the tradeoffs involved when designing a directory-based protocol that implements coherent shared memory through a combination of hardware and software mechanisms. The fundamental design decisions involve ... -
Space - Time Scheduling of Instruction-Level Parallelism on a Raw Machine
(1997-12)Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocessors are ill-suited to exploit such advances. ... -
UDM: User Direct Messaging for General-Purpose Multiprocessing
(1996-03)User Direct Messaging (UDM) allows user-level, processor-to- processor messaging to coexist with general multiprogramming and virtual memory. Direct messaging, where processors launch and receive messages in tens of cycles ...
