A 16-bit, 100kS/s self-calibrating cyclic analog-to-digital converter

Author(s)
Guidry, Michael J. (Michael James), 1976-
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Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Advisor
Hae-Seung Lee.
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Abstract
Self-calibrating AID architectures minimize the sometimes expensive process of in-factory calibration, thus allowing manufacturers to reduce chip cost. This thesis presents an AID converter built using one such architecture, the reference-refreshing architecture. This converter shows under simulation 100 kHz performance at 16 bits, with INL of 1.2 LSBs, SNR of 89 dB, and power consumption of 170 mW.
Description
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
 
Includes bibliographical references (leaf 50).
 
Date issued
2000
URI
http://hdl.handle.net/1721.1/9075
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.
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