dc.contributor.author | Yip, Marcus | |
dc.contributor.author | Bohorquez, Jose L. | |
dc.contributor.author | Chandrakasan, Anantha P. | |
dc.date.accessioned | 2015-02-24T20:00:24Z | |
dc.date.available | 2015-02-24T20:00:24Z | |
dc.date.issued | 2012-06 | |
dc.identifier.isbn | 978-1-4673-0849-6 | |
dc.identifier.isbn | 978-1-4673-0848-9 | |
dc.identifier.isbn | 978-1-4673-0845-8 | |
dc.identifier.uri | http://hdl.handle.net/1721.1/95487 | |
dc.description.abstract | This paper presents a mixed-signal ECG front-end that uses aggressive voltage scaling to maximize power-efficiency and facilitate integration with low-voltage DSPs. 50/60Hz interference is canceled using mixed-signal feedback, enabling ultra-low-voltage operation by reducing dynamic range requirements. Analog circuits are optimized for ultra-low-voltage, and a SAR ADC with a dual-DAC architecture eliminates the need for a power-hungry ADC buffer. Oversampling and ΔΣ-modulation leveraging near-V[subscript T] digital processing are used to achieve ultra-low-power operation without sacrificing noise performance and dynamic range. The fully-integrated front-end is implemented in a 0.18μm CMOS process and consumes 2.9μW from 0.6V. | en_US |
dc.description.sponsorship | Texas Instruments Incorporated | en_US |
dc.description.sponsorship | Natural Sciences and Engineering Research Council of Canada (Fellowship) | en_US |
dc.language.iso | en_US | |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1109/VLSIC.2012.6243792 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | Chandrakasan | en_US |
dc.title | A 0.6V 2.9µW mixed-signal front-end for ECG monitoring | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Yip, Marcus, Jose L. Bohorquez, and Anantha P. Chandrakasan. “A 0.6V 2.9µW Mixed-Signal Front-End for ECG Monitoring.” 2012 Symposium on VLSI Circuits (VLSIC) (June 2012). | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.contributor.approver | Chandrakasan, Anantha P. | en_US |
dc.contributor.mitauthor | Yip, Marcus | en_US |
dc.contributor.mitauthor | Chandrakasan, Anantha P. | en_US |
dc.relation.journal | Proceedings of the 2012 Symposium on VLSI Circuits (VLSIC) | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
dspace.orderedauthors | Yip, Marcus; Bohorquez, Jose L.; Chandrakasan, Anantha P. | en_US |
dc.identifier.orcid | https://orcid.org/0000-0002-5977-2748 | |
mit.license | OPEN_ACCESS_POLICY | en_US |
mit.metadata.status | Complete | |