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dc.contributor.authorYip, Marcus
dc.contributor.authorBohorquez, Jose L.
dc.contributor.authorChandrakasan, Anantha P.
dc.date.accessioned2015-02-24T20:00:24Z
dc.date.available2015-02-24T20:00:24Z
dc.date.issued2012-06
dc.identifier.isbn978-1-4673-0849-6
dc.identifier.isbn978-1-4673-0848-9
dc.identifier.isbn978-1-4673-0845-8
dc.identifier.urihttp://hdl.handle.net/1721.1/95487
dc.description.abstractThis paper presents a mixed-signal ECG front-end that uses aggressive voltage scaling to maximize power-efficiency and facilitate integration with low-voltage DSPs. 50/60Hz interference is canceled using mixed-signal feedback, enabling ultra-low-voltage operation by reducing dynamic range requirements. Analog circuits are optimized for ultra-low-voltage, and a SAR ADC with a dual-DAC architecture eliminates the need for a power-hungry ADC buffer. Oversampling and ΔΣ-modulation leveraging near-V[subscript T] digital processing are used to achieve ultra-low-power operation without sacrificing noise performance and dynamic range. The fully-integrated front-end is implemented in a 0.18μm CMOS process and consumes 2.9μW from 0.6V.en_US
dc.description.sponsorshipTexas Instruments Incorporateden_US
dc.description.sponsorshipNatural Sciences and Engineering Research Council of Canada (Fellowship)en_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/VLSIC.2012.6243792en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceChandrakasanen_US
dc.titleA 0.6V 2.9µW mixed-signal front-end for ECG monitoringen_US
dc.typeArticleen_US
dc.identifier.citationYip, Marcus, Jose L. Bohorquez, and Anantha P. Chandrakasan. “A 0.6V 2.9µW Mixed-Signal Front-End for ECG Monitoring.” 2012 Symposium on VLSI Circuits (VLSIC) (June 2012).en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.approverChandrakasan, Anantha P.en_US
dc.contributor.mitauthorYip, Marcusen_US
dc.contributor.mitauthorChandrakasan, Anantha P.en_US
dc.relation.journalProceedings of the 2012 Symposium on VLSI Circuits (VLSIC)en_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dspace.orderedauthorsYip, Marcus; Bohorquez, Jose L.; Chandrakasan, Anantha P.en_US
dc.identifier.orcidhttps://orcid.org/0000-0002-5977-2748
mit.licenseOPEN_ACCESS_POLICYen_US
mit.metadata.statusComplete


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